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Advanced Packaging (3D-IC's)

STSV1CUTEOS: Through Silicon Via Cu Integration Test Wafer

TSV test wafers for 3D-IC integration

  • 2um - 100um Via Sizes
  • 2um - 1000um Line Sizes
  • 2um - 50um Box Trench width
  • CMP configuration with 5um deep etching and 10um ECP Cu fill.


 

   
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